Integrated circuits are ubiquitous in modern electronic devices and systems. These devices and systems are highly complex and are very difficult to design and manufacture. The designs routinely involve tens, hundreds, or even thousands of people, distributed geographically and across many time zones. The devices and systems are manufactured via a complicated, multi-step process including photolithographic printing and chemical processing, along with many handling steps. The number of manufacturing steps can run easily into the thousands. Modern systems contain a variety of circuits, including digital, analog, and high frequency components, which further complicates the design and manufacturing processes. Feature sizes of the circuitry that make up modern devices and systems are now routinely smaller than the wavelength of visible light. As feature sizes of the components continue to decrease, more circuitry and features are added into the designs. For example, device counts for logic systems commonly run to the tens or hundreds of millions of active devices (e.g. transistors). In addition, the rapid changes in market demand drive ever-increasing circuit performance and device count, chip feature sets, system versatility and flexibility, and a variety of other system demands. These demands impose often-contradictory requirements on the design process, making the design process highly complex and expensive. Each design decision has a profound impact on the resulting device or system design. Requirements regarding system performance, physical size, architectural complexity, power consumption, heat dissipation, fabrication complexity and cost, for example, influence a design. To handle electronic system design complexity, designers create a design specification to which their electronic systems are designed. The specification is created to balance the many disparate system demands required of the electronic system, and to contain otherwise exploding design complexity. For a design to be considered valid, that design must match the numerous and diverse requirements of the design's specification.
Verifying that a design matches its system specification is a highly complex and time-consuming process. Static verification tools are routinely employed to test designs against a specification. In part, static testing is becoming increasingly complex because system size and design complexity continue to grow. In addition, different design techniques, methodologies, and standards require tests which cater to different systems requirements. As a result, static test tools often find and report copious numbers of violations. The violations may be due to design errors, design violations, process violations, and so on. Reports of violations at a block level may run to tens of thousands of violations, while reports for full chips may run to the millions of violations. Analysis and validation of reports from static verification tools pose challenges because of the sheer volume of data that must be handled and analyzed. Rapid turn around time (TAT) is key in bringing a design to market, so expedient analysis of the static checker report of violations is critical to the design process. Verification of static check violation reports is often a key design sign-off criterion. Thus, designers need to selectively analyze violations—basing their violation selections on an educated guess or previous experience—in order to analyze the violations based on the severity of a report and the relative importance of a check. This process is time consuming and tedious, and as a result, the values of the many other checks performed by the static tool remain undermined, opening the designer to the risk that he or she chose to analyze the incorrect violations and thus suppressed the discovery of an actual design bug. In addition, it is imperative that analysis of violations generated by the static tool be performed in a computationally efficient and cost effective manner.